Advanced Diploma in ASIC Design - RTL Verification

Foundation topics7 topics

• Overview of transistor theory and network analysis
• Introduction to Linux and scripting
• Advanced Logic Design techniques
• Concept to Chip-design flow for small, large and analog mixed-signal designs
• DSM IC Fabrication Flow
• Fundamentals of RTL-D and Verification using Verilog
• Fundamentals of Static Timing Analysis

SystemVerilog11 topics

• Introduction to SV and the ASIC flow
• Commonly used terminologies in SV
• SV data types
• Object-Oriented Programming (OOP) concepts
• SV stratified event queue / scheduler
• SV tasks and functions
• Verification-specific SV constructs
• Functional coverage
• Verification plan and SV testbench architecture
• Modelling testbench blocks
• Assertions

UVM11 topics

• Introduction to UVM
• UVM testbench architecture
• Simulation phases in UVM
• UVM reporting
• UVM factory
• UVM configuration
• UVM transaction
• UVM stimulus
• Transaction Level Modeling (TLM)
• UVM analysis components
• UVM RAL model

Final projectHands-on

In the project phase you work on multiple projects covering verification planning, modelling SV and UVM testbenches, building SV/UVM testbench environments, and verifying protocols such as Ethernet and SATA. You also develop test cases and migrate test environments.