Introduction to VHDL (IHDL110)

Course Description

This one-day class is a general introduction to the VHDL language and its use in programmable logic design, covering constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of VHDL so that you can begin creating your own designs, using both behavioral and structural approaches.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

Introduction to Verilog (IHDL120)

Course Description

This class is a general introduction to the Verilog language and its use in programmable logic design, covering the basic constructs used in both the simulation and synthesis environments. By the end of this course, you will have a basic understanding of the Verilog module, data types, operators and assignment statements needed to begin creating your own designs, using both behavioral and structural approaches.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

ADVANCED DIPLOMA IN ASIC DESIGN - FULL CUSTOM

Course Description:

Learn and Create a Rewarding Career in IC MASK Layout Design

ADAD Full Custom is designed to make you a competent and productive Analog Layout Engineer. The course enables you to acquire knowledge, skills and practical experience across the entire backend Full Custom Flow (Circuit to tape-out). The course covers key fundamental concepts of ASIC Physical Design methodology which will enhance the employability of the students.

The “In Class” Sessions, Lab exercises and Industry Standard Projects that our students are put through instills confidence and the analytical abilities required to work on complex industry’s challenges in various Deep Sub-Micron Technology Process. Exposure to the use of Physical Design tools familiarity with timing closure and related topics are covered.
 

Highlights:

1. ADAD Full Custom - 6 months full time flagship program in VLSI

2. Participative & Experiential Learning Model

3. 25% time spent on theory

4. 75% time spent in Labs and Real Life Projects

5. Access to Semiconductor Technology

6. Work and Learn in EDA Tools used by the Industry

7. Corporate Practice Environment

Topics Covered:

1. Overview of transistor theory and network analysis

2. Introduction to Linux and scripting

3. Advanced Logic Design techniques

4. Concept to Chip design flow for small, large and analog mixed signal designs

5. DSM IC Fabrication Flow

6. Fundamentals of RTL-D and Verification using Verilog

7. Fundamentals of Static Timing Analysis

8. Using physical IP in a PD Environment.

Domain Specific Topics

1. Introduction to Full custom Design Flow

2. Review of Foundary documents and IC fabrication steps

3. Layout design and optimisation techniques for DSM process nodes

4. Layout design of active and passive components

5. Layout matching and optimization techniques

6. DFM, DRC/LVS, PEX and Back annotation flows

7. ESD, LUP and tape-out Flow

Project : Layout Design of Physical IP, Memory and Analog layouts

Placement Opportunities.

Our placement record in VLSI has been an impressive 90%.

After completion of this course you may be eligible to apply for Backend full custom layout design jobs.

Companies visit us regularly to hire qualified students. Intel, Broadcom, IBM, Cypress, Mentor Graphics, Synopsys, Synapse, KPIT Cummins, Tata Elxsi, Wipro, HCL, Infosys are few among many companies who regularly acquire Talent from us through our campus placement drives

LINUX FOR VLSI ENGINEERS

Advanced Diploma in Embedded Systems Software

Course Description

ADEMS is a 16 weeks full time program designed to meet the requirements of the current job market. The program comprises of two phases. Phase one covers the fundamental concepts in Embedded Systems and domain specific modules. Phase two is the project phase where you get an opportunity to apply design concepts learnt in phase one by working on real life projects under the supervision of industry experts. The contents of the course are designed to make you eligible to apply for hardware designer, software developer, firmware developer and network stack developers job openings. A key differentiator of our program is the introduction of advanced microcontrollers and use of multiple hardware boards in the course.

Phase One

Introduction to Embedded System Design & Hardware Subsystem

Hardware software Integration

Advanced Hardware software co design & Embedded Linux

Project Domains:

Hardware Software Integration

Hardware and software used

Duration: 4 months full-time program

Course Description
 

Our flagship VLSI program, it covers FPGA, ASIC Frontend, ASIC Backend and Full Custom design methodologies giving you an option to specialize as a RTL Verification Engineer, ASIC Physical Design Engineer or Full Custom Memory and/or Physical IP Engineer. To the best of our knowledge no other skill development program in India cover all these  domains
 

• Students who gain admission to this program are job ready for FPGA, ASIC and/or Full-custom Analog domains
   

• Product companies, Service companies, EDA tools providers and IP companies regularly visit our campus to hire engineers who have successfully completed this program
   

• We have one of the best placement assistance programs; enquire at the center for details.
   

• Duration: 6 months full-time program.
   

• Please enquire at the center for other details.

Advanced Timing Analysis with TimeQuest (IDSW125) 

Course Description

In this class,youwill improve your proficiency in writing Synopsys Design Constraint (SDC) files and performing timing analysis using the TimeQuest timing analyzer in the Quartus® II software v. 11.1. You will also learn how to automate the process of constraining and analysis by writing customized Tcl script files.

Course Fee

• International (Corporate) Fee: $495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

Best Practices for Maximizing FPGA Design Productivity (2 Day Course)  (IPRO200)

Course Description

Learn the best ways to maximize productivity throughout the FPGA design cycle, while also maximizing design performance. Using a recommended design methodology as a framework, see what is involved at a high level in preparing to create an FPGA design and what is required to implement it - from the creation of the design specification all the way to final sign-off.

Course Fee

• International (Corporate) Fee: $990

• Domestic (Corporate) Fee: INR 10,000

• Domestic (Student) Fee: INR 5,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

The Quartus II Software Design Series: Optimization (IDSW140)

Course Description

In this class,youwill learn advanced features of the Quartus® II design software v.11.1 that will enable you to shorten your design cycle as well as improve your design performance and utilization.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

 Designing with the Nios II Processor and Qsys (2 Day Course)  (IHDL115)

Course Description

This course will teach you how to design in a soft core embedded processor with an Altera FPGA. This course is focused on the hands-on development of Nios® II processor-based systems using a Nios II Development Kit. You will learn how to integrate a Nios II 32-bit microprocessor and test it in an Altera FPGA. 

Course Fee

• International (Corporate) Fee: $ 990

• Domestic (Corporate) Fee: INR 10,000

• Domestic (Student) Fee: INR 5,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

Developing Software for the Nios II Processor (2 Day Course) (IEMB230)

Course Description

This course is targeted at Software Engineers or Developers. You will learn to develop and run embedded software for the Nios® II processor in the Nios II Software Build Tools for Eclipse and with the Nios II Command Tools.

Course Fee

• International (Corporate) Fee: $ 990

• Domestic (Corporate) Fee: INR 10,000

• Domestic (Student) Fee: INR 5,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

System Integration with Qsys (2 Day Course) (IQSYS100) 

Course Description

This class will teach you how to quickly build designs for Altera FPGAs using Altera’s Qsys system-level integration tool. You will learn how to build hierarchical systems, how to quickly integrate IP and custom logic into a system, and also how to optimize designs for performance. Since Qsys makes design reuse easy through standard interfaces, we will dive deeply into the Avalon-Memory Mapped and Streaming Interfaces.

Course Fee

• International (Corporate) Fee: $ 990

• Fee: INR 10,000

• Domestic (Student) Fee: INR 5,500

For further details contact RV-VLSI

RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

 Advanced VHDL Design Techniques  (IHDL240) 

Course Description

In this class,youwill learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

The Quartus II Software Design Series: Timing Analysis  (IDSW120) 

Course Description

In this class, you will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the Quartus® II software v. 11.1. You will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you meet those requirements.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

Advanced Verilog HDL Design Techniques (IHDL230) 

Course Description

In this class,youwill learn & practice efficient coding techniques for writing synthesizable VHDL for programmable logic devices (FPGAs & CPLDs). While the concepts presented will mainly target Altera® FPGA devices using the Quartus® II software, many can be applied to other devices & synthesis tools.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

The Quartus II Software Design Series: Foundation (2 Day Course) (IDSW110)

Course Description

By attending The Quartus II Software Design Series: Foundation course, you'll learn how to use the Quartus® II software v11.1 to develop an FPGA or CPLD design from initial design to device programming.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

The Quartus II Software Design Series: Debug and Analysis Tools (IDSW135)

Course Description

In this class, you will learn features of the Quartus® II software v. 11.1 that will enable you to analyze and debug your Altera® design. You will get to understand power analysis tools, and other tools like Simultaneous Switching Noise (SSN) Analyzer, SignalTap® II embedded logic analyzer, Signal Probe & the Logic Analyzer Interface. You will learn to analyze and make changes to your design using the Chip Planner.

Course Fee

• International (Corporate) Fee: $ 495

• Domestic (Corporate) Fee: INR 5,000

• Domestic (Student) Fee: INR 3,500

For further details contact RV-VLSI

In an effort to maintain quality, RV-VLSI reserves the right to change or modify the course content and the duration of the course and the course fees.

ADVANCED DIPLOMA IN ASIC DESIGN - RTL VERIFICATION

Course Description:

Learn and Create a Rewarding Career in RTL Verification

ADAD frontend Verification is designed to make you a competent and productive VLSI Verification Engineer. The course enables you to acquire knowledge, skills and practical experience in RTL Verification using System Verilog and UVM.

The “In Class” Sessions, Lab exercises and Industry Standard Projects that our students are put through instills confidence and the analytical abilities required to work on complex industry’s challenges in various Deep Sub-Micron Technology Process.
 

Highlights:

1. ADAD RTL Verification - 4 months full time flagship program 

2. Participative & Experiential Learning Model

3. 25% time spent on theory

4. 75% time spent in Labs and Real Life Projects

5. Access to Semiconductor Technology

6. Work and Learn in EDA Tools used by the Industry

7. Corporate Practice Environment

Foundation Topics Covered:

1. Overview of transistor theory and network analysis

2. Introduction to Linux and scripting

3. Advanced Logic Design techniques

4. Concept to Chip design flow for small, large and analog mixed signal designs

5. DSM IC Fabrication Flow

6. Fundamentals of RTL-D and Verification using Verilog

7. Fundamentals of Static Timing Analysis

DOMAIN SPECIFIC TOPICS:

SYSTEM VERILOG TOPICS

1. Introduction to SV and the ASIC Flow

2. Commonly Used Terminologies in SV

3. SV Data Types

4. Object-Oriented Programming (OOP) Concepts

5. SV Stratified Event Queue/Scheduler

6. SV Tasks and Functions

7. Verification Specific SV Constructs

8. Functional Coverage

9. Verification Plan and SV Testbench Architecture

10. Modelling Testbench Blocks

UVM TOPICS

1. Introduction to UVM

2. UVM Testbench Architecture

3. Simulation phases in UVM

4. UVM Reporting

5. UVM Factory

6. UVM Configuration

7. UVM Transaction

8. UVM Stimulus

9. Transaction Level Modeling (TLM)

10. UVM Analysis Components

Final Project : During the project phase students will work on multiple projects involving, Verification planning, Modeling SV testbenches , Modeling UVM Testbenches. Development of SV or UVM Testbench Environment and Verification of different protocols such as Ethernet, SATA etc . Developing testcases and migrating the test environments

Placement Opportunities.

Our placement record in VLSI has been an impressive 90%.

After completion of this course you will be eligible to apply for Frontend RTL Verification jobs.

Companies visit us regularly to hire qualified students. Intel, Broadcom, IBM, Cypress, Mentor Graphics, Synopsys, Synapse, KPIT Cummins, Tata Elxsi, Wipro, HCL, Infosys are few among many companies who regularly acquire Talent from us through our campus placement drives

ADVANCED DIPLOMA IN ASIC DESIGN - PHYSICAL DESIGN

Course Description:

Learn and Create a Rewarding Career in ASIC Physical Design

ADAD Physical Design is designed to make you a competent and productive Physical Design Engineer. The course enables you to acquire knowledge, skills and practical experience across the entire Backend ASIC Flow (Netlist to GDSII).

The “In Class” Sessions, Lab exercises and Industry Standard Projects that our students are put through instills confidence and the analytical abilities required to work on complex industry’s challenges in various Deep Sub-Micron Technology Process Nodes.
 

Highlights:

1. ADAD Physical Design - 6 months full time flagship program in VLSI

2. Participative & Experiential Learning Model

3. 25% time spent on theory

4. 75% time spent in Labs and Real Life Projects

5. Access to Semiconductor Technology

6. Work and Learn in EDA Tools used by the Industry

7. Corporate Practice Environment

Topics Covered:

1. Overview of transistor theory and network analysis

2. Introduction to Linux and scripting

3. Advanced Logic Design techniques

4. Concept to Chip design flow for small, large and analog mixed signal designs

5. DSM IC Fabrication Flow

6. Fundamentals of RTL-D and Verification using Verilog

7. Fundamentals of Static Timing Analysis

Domain Specific Topics

1. Introduction to the ASIC Flow

2. Design Setup and design automation

3. Chip-Level and Blocl-level implementation steps

4. Floorplan and power planning

5. Placement and Clock Tree Synthesis

6. Routing, Physical Verification DRC, LVS and DFM checks

7. Signal Integrity and Backannotation

8. Sign-off checks and Tapeout

Placement Opportunities.

Our placement record in VLSI has been an impressive 90%.

After completion of this course you will be eligible to apply for ASIC Physical Design Engineer jobs.

Companies visit us regularly to hire qualified students. Intel, Broadcom, IBM, Cypress, Mentor Graphics, Synopsys, Synapse, KPIT Cummins, Tata Elxsi, Wipro, HCL, Infosys are few among many companies who regularly acquire Talent from us through our campus placement drives

RTL DESIGN USING VERILOG (BRIDGE COURSE FOR NON VLSI ENGINEERS)

Course Description

Designing a VLSI chip using FPGA's are very popular these days.

This program is a foundation course for working professionals looking for a job change to the core industry and for engineers in the core industry looking for a lateral change. This program introduces you to the concepts of system design, RTL design using Verilog, programmable ASICs and the role of programmable ASICs in design and development of high density complex IP designs. The course also focuses on the real and practical scenarios using modern FPGA architectures. The course will conclude with an industry oriented project work under the supervision of our expert leads

Pre-requisites

• Understanding of Logic Design concepts
• Familiarity with Verilog Syntax

 Who will Benefit

• BE (Elens and related branches), Engineers working in software domain looking for core jobs
• VLSI Engineers seeking lateral shift to a front end job.

Course Content

1. Overview of Digital Logic Design
2. Introduction to  Verilog HDL
3. Advanced Verilog Design Techniques
4. Basics of Programmable Logic
5. How to begin Simple FPGA Design
6. Design Implementation using Altera Quartus II
7. Efficient Design Practices using Altera Quartus II
8. Project work and board bring up

Course Fee and Duration:

12 days, Rs. 25,000 +Taxes

RTL VERIFICATION USING SYSTEM VERILOG

Course Overview

1. Familiarity with Logic Design concepts
2. Familairity with Verilog Syntax
3. Prior knowledge of RTL Verification concepts using Verilog is desirable

1. VLSI Engineers seeking lateral shift from FPGA to ASIC front-end jobs
2. Engineers looking for RTL verification jobs.
3. Engineers familiar with RTL verification using Verilog looking to acquire skills in System Verilog.

Course Content

1. Introduction to SV
2. Commonly Used Terminologies in SV
3. Data Types
4. Object-Oriented Programming (OOP) Concepts
5. SV Stratified Event Queue/Scheduler
6. SV Tasks and Functions
7. Verification Specific SV Constructs
8. Functional Coverage
9. Verification Plan and SV Testbench Architecture
10. Modelling Testbench Blocks

Course Fee and Duration:

12 days, Rs.48,000+ Taxes

IC LAYOUT DESIGN AND OPTIMIZATION TECHNIQUES (FULL CUSTOM LAYOUT DESIGN).

1. Basic undestanding of MOS Transistor operation

1. VLSI Engineers seeking lateral shift as Full Custom/Mask Layout Engineer
2. Engineers looking to work in areas like Physical IP & Full Custom Analog Layout   design

1. Overview of Full custom IC design
2. Review of Simple circuits
3. Overview of  IC Fabrication Process
4. Introduction to Polygon Editors
5. Layout design concepts
6. Introduction to ESD, LUP, Device Matching techniques and PDK’s
7. Physical Verification and Parasitic Extraction
8. Project Work

STATIC TIMING ANALYSIS OF VLSI DESIGNS

1. Logic Design
2. MOS Transistor Theory

1. VLSI Engineers seeking lateral shift to a back end job.
2. Engineers looking to work for Block level Physical Design Implementation, Place and Route  job profiles.

1. Concepts of STA
2. Clocks & Virtual Clocks
3. Operating Conditions, 
4. Analysis of various Modes & Corners
5. Analyzing  the Timing Reports
6. Signal  Integrity

ASIC PHYSICAL DESIGN (PD) FOR DEEP SUBMICRON PROCESS NODES

Course Overview :

The last phase in the ASIC Design flow involves designing the layout of a Gate Level Netlist using Automatic Place and Route  (AP&R) Tools

 This program introduces you to the concepts used to design Chip-level and Block Level ASIC Layoutsfor Deep sub-micron process nodes using industry standard AP&R (Synopsys) tools. The various implementation steps from Netlist to GDS2 will be covered in detail. Every participant will get the opportunity to practice concepts taught in the class during the concept labssessions. The course will conclude with a project done under the supervision of our leads.

Pre Requisites

1. Logic Design

2. Course on Static Timing Analysis

Who will Benefit

1. VLSI Engineers seeking lateral shift to a back end job.

2. Engineers looking to work for  Block level Physical Design Implementation, Place and Route job domains.

Course Content

1. Introduction to the ASIC Flow

2. Design Setup

3. Chip-Level and Blocl-level implementation steps

4. Floorplan and power planning

5. Placement and Clock Tree Synthesis,

6. Routing, Physical Verification and DFM checks

7. Signal Integrity and Backannotation

8. Sign-off checks and Tapeout

Course Fee and Duration

16 days, Rs.62,000+Taxes

Industry standard sign-off tools from multiple EDA vendors.

All courses will be delivered by VLSI professionals with hands on experience taping out multiple chips used in industry. 

ADVANCED DIPLOMA IN EMBEDDED SYSTEMS SOFTWARE (ADEMS)
 

• Advanced C and Coding Standards
• C++ and Data Structures
• Operating System Essentials (Linux)
• Computer Architecture and System Design using Micro-controller and SoC    
  
   

• Linux Internals and Systems Programming
• Board Support Package (BSP) Development and OS Porting
  
   

• Kernel Programming and Device Drivers
• Hardware Integration and Application Development
  
   

• Product Development Life Cycle
• Documentation Standards
• Organizational Hierarchy